1. Field of the Invention
The present invention relates to integrated circuits, and more particularly to lightly doped drain insulated-gate field-effect transistors.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate electrode to control an underlying surface channel joining a source and a drain. The channel, drain and source are located in a semiconductor substrate, with the substrate being doped oppositely to the drain and source. The gate electrode is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate electrode, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and drain are formed by introducing dopants of a second conductivity type (P or N) into the semiconductor substrate of a first conductivity type (N or P) using a patterned gate as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate electrode and the source/drain regions. Heavily doped polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films are used as the gate electrode. Since polysilicon has the same high melting point as a silicon substrate, it can be deposited prior to source and drain formation. The polysilicon is anisotropically etched through openings in a photoresist mask to provide a gate electrode which provides a mask during formation of the source and drain by ion implantation. Photolithography is frequently used to create patterns in the photoresist mask that define the gate electrode.
Photolithographic systems often use a radiation source and a lens in conjunction with a mask or reticle to selectively irradiate the photoresist. The radiation source projects radiation through the mask or reticle to the lens, and the lens focuses an image of the mask or reticle onto a wafer. A mask transfers a pattern onto the entire wafer (or another mask) in a single exposure step, whereas a reticle transfers a pattern onto only a portion of the wafer. The three major methods of optically transferring a pattern on a mask or reticle to a photoresist coated wafer include contact printing, proximity printing and projection printing. In general, the term "resolution" describes the ability of an optical system to distinguish closely spaced objects. The minimum resolution of a photolithographic system is the dimension of minimum linewidth or space that the machine can adequately print or resolve. While optical photolithography continues to be the dominant technology because it is well established and is capable of implementing sub-micron resolution of at least 0.35 microns using current equipment, there are incentives for trying to push the current optical photolithography technology into significantly better patterning capabilities for more precise fabrication.
In recent years, with larger and larger scale semiconductor integrated circuit devices (IC's), IGFETs used as circuit elements have become scaled down. This, however, has not been simply accompanied by appropriate supply voltage scaling because interfaces between IC circuit devices must be standardized. As IGFET dimensions are reduced and the supply voltage remains constant (e.g., 3V), the electric field in the gate insulator tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, hot electrons can overcome the potential energy barrier between the silicon substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator accumulates over time and can lead to a permanent change in the threshold voltage of the device and premature dielectric breakdown.
A number of techniques have been utilized to reduce hot carrier effects. The voltages applied to the device can be decreased or appropriate drain engineering design techniques, which result in special drain structures that reduce hot electron effects, can be implemented. One such technique is a lightly doped drain (LDD). LDDs absorb some of the potential into the drain and thus reduce the maximum electric field. The drain is typically formed by two ion implants. One of these is self-aligned to the gate electrode, and the other is self-aligned to the gate electrode on which sidewall spacers have been formed. The spacers are typically oxides. The purpose of the lighter first dose is to form a lightly doped region of the drain (or LDD) at the sidewall near the channel, which can reduce the maximum electric field. The second heavier dose forms a low resistivity region of the drain, which is subsequently merged with the lightly doped region. Thereafter, electrical contacts are formed on the heavily doped region. Since the heavily doped region is farther away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics. The lightly doped region is not necessary for the source (unless bi-directional current is used), however LDD structures are typically formed for both the drain and source to avoid the need for an additional masking step.
Disadvantages of LDDs are their increased fabrication complexity compared to conventional drain structures, and parasitic resistance. LDDs exhibit relatively high parasitic resistance due to their light doping levels. During operation, the LDD parasitic resistance can decrease drain current, which in turn may reduce the speed of the IGFET. The saturation drain current is affected little by the parasitic resistance of the drain region and greatly by the effective gate voltage drop due to the parasitic resistance of the source region. Reduction of the drain current can, therefore, be decreased by implementation of an non-symmetrical LDD-IGFET with a lightly doped region only at the drain. However, a non-symmetrical LDD-IGFET can further increase fabrication complexity.
One method for non-symmetrical LDD-MOSFET fabrication is U.S. Pat. No. 5,424,229 entitled "Method For Manufacturing MOSFET Having An LDD Structure" (Oyamatsu) which includes masking the substrate before the gate electrode is formed and leaving a window open in the mask. The lightly doped drain region is then implanted at an angle into the substrate through the window opening. The mask is removed and the gate electrode is formed in the window opening and over a portion of the lightly doped drain region. The heavily doped regions are then formed aligned with the sidewalls of the gate electrode. However, implanting doped regions at an angle into the substrate increases fabrication complexity.
Another method is U.S. Pat. No. 5,286,664 entitled "Method For Fabricating The LDD-MOSFET" (Horiuchi) wherein the gate electrode is formed and then one half of the gate electrode (on the source side) is masked with a photoresist mask. The lightly doped drain region is implanted. Then a single spacer is formed on the drain side using a liquid phase deposition (LPD) method for depositing silicon dioxide. The mask is then removed and the heavily doped regions are implanted. The LPD method however is not precise and can make controlling the thickness or size of the spacer difficult.
Accordingly, there is a need for a non-symmetrical LDD-IGFET which decreases the parasitic resistance, therefore increasing drain current, yet which can be simply and precisely fabricated.